Portable personal computers have generated a large demand for low power integrated circuits. The utilization of low power integrated circuits (i.e., 3.3 volts) within portable systems, such as a laptop personal computer, provides reduced consumption and longer battery life. However, some 5 volt integrated circuits provide performance advantages over low power 3.3 volt integrated circuits. Therefore, both 5 volt integrated circuits and 3.3 volt integrated circuits may be utilized within a single personal computer.
An input/output buffer may be utilized intermediate mixed voltage logic circuits. Several problems may arise when 3.3 volt and 5 volt integrated circuits are intermixed within a single device. For example, 3.3 volt integrated circuits usually have a thin MOS gate oxide compared with the 5 volt integrated circuit (70A versus 90A). The MOS gate oxide of 3.3 volt circuits may become leaky when a 5 volt input signal is applied to it. The MOS gate oxide may become leaky due to tunneling effect or time-dependent dielectric breakdown (TDDB) effect. The gate oxide might also be permanently damaged if the electric field in the oxide is larger than its breakdown voltage.
Another problem is leakage current from a 5 volt pad interconnect to the input/output buffer power supply via a parasitic junction diode of the PMOS transistor. A third problem is the leakage current caused by higher static current due to 5 volts on the respective drains of the 3.3 volt powered PMOS and NMOS. A final problem is the leakage current from the electrostatic discharge (ESD) protection diode on the driven input buffer. Other reliability issues which may arise with the mixing of 3.3 volt and 5 volt integrated circuits include hot carrier effect and electromigration due to the higher pad voltage (i.e. 5 volts) on the respective drains of the output metal-oxide semiconductor transistors.
A cascade output NMOS transistor may be utilized to protect an NMOS output transistor of the input/output buffer to eliminate or minimize many of the aforementioned design problems.
Referring to FIG. 1, a prior art input/output buffer 10 having an NMOS output transistor 11 and a PMOS output transistor 13 is shown coupled with a pad 14. The NMOS output transistor 11 is coupled with a cascade NMOS output transistor 12. The channel width and length (W/L) ratio within each of the cascaded NMOS output transistors 11, 12 is doubled (compared to the width and length ratio of a single output NMOS transistor) to maintain the original driving strength.
The prior art I/O buffer 10 shown in FIG. 1 minimizes some of the design problems and tolerates a 5 volt input data signal on the pad 14. However, the prior art I/O buffer 10 is not a true CMOS buffer inasmuch as its output PMOS transistor 13 and output NMOS transistor 11 are not fully turned off when the output data signal is changed from low to high and high to low, respectively.
The graph shown in FIG. 2 illustrates that the voltages on the gates of the output NMOS transistor 11 and the output PMOS transistor 13 (represented by respective lines 16 and 17 in FIG. 2) are not equal from before and after switching in response to changes of an output data signal (represented by line 15).
The utilization of the drain voltage from the output NMOS transistor 11 to control the gate voltage of the output PMOS transistor 13 results in the inequality of the gate voltages of the output NMOS transistor 11 and the output PMOS transistor 13. This inequality during switching is shown in FIG. 2 and draws unnecessary current which increases power consumption.
Therefore, there exists an increased need for a buffer which operates as a true CMOS buffer within a mixed voltage signaling environment.